Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed operations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
In a conventional semiconductor package, an encapsulant is deposited over a semiconductor die or an insulating layer is formed over the semiconductor die and a temporary carrier as a reconfigured or reconstituted wafer. For example, encapsulant can be deposited over the semiconductor die and carrier by mold injection or can be applied using a compression molding process. Similarly, insulating layers may be built up or formed over the carrier to embed the semiconductor die. Thereafter, the carrier is removed to expose the semiconductor die. A build-up interconnect structure, comprising one or more conductive layers, is typically formed over the exposed semiconductor die for electrical redistribution. A build-up interconnect structure may also be formed around the semiconductor die. In either case, providing 3D vertical electrical interconnect through a conventional semiconductor package often requires the formation of multiple layers around the semiconductor die, formation of vias by, e.g., laser drilling, and deposition of conductive material in the vias.
The semiconductor die is known to vertically and laterally shift during encapsulation, particularly during mold injection, which can cause misalignment of the build-up interconnect structure. Further, a mismatch between the coefficient of thermal expansion (CTE) of the encapsulant and carrier can cause warpage in the reconfigured wafer. A CTE difference between the encapsulant and semiconductor die can cause delamination due to thermal stress. Encapsulation for embedded wafer level ball grid array (eWLB) fabrication requires very fine volume control and generates low throughput due to lengthy molding cure times. Forming an insulating layer over the semiconductor die can attract foreign materials, generate wasteful byproducts, and requires excess manufacturing steps with increased cost. Forming an insulating layer over a semiconductor die can further result in roughened surfaces around the insulating layer. The roughened surfaces can impact adhesion between the insulating layer and additional components disposed on the insulating layer. The roughened surfaces can further impact the electrical characteristics of conductive layers formed on the insulating layer as part of the build-up interconnect structure. For example, when a conductive layer is applied over the roughened surfaces for redistribution, the interface between the insulating layer and conductive layer lacks linearity, i.e., contains imperfections along the interface due to the roughened surfaces of the insulating layer. Imperfections along the interface can cause higher resistance, poorer transmission quality, and degrade redistribution performance across the conductive layer. In addition, forming vertical interconnect structures in a semiconductor package by forming vias and filling the vias with conductive material requires specialized manufacturing procedures, numerous fabrication steps, and increased cost.